The '378 application discloses a parallel test circuit with active devices. A high-level representation of an exemplary one of the parallel test circuits disclosed in the '378 application is shown in FIG. 7. The parallel test circuit 700 utilizes a channel input/output (I/O or IO) block 702 and four DUT I/O blocks 704, 706, 708, 710 to fan-out/fan-in a signal by four (i.e., 1:4 or 4:1) between a TESTER_IO node and four DUT_IO nodes (DUT_IO_0, DUT_IO_1, DUT_IO_2 and DUT_IO_3).
Each of the channel and DUT I/O blocks 702, 704, 706, 708, 710 comprises an active driver and an active receiver. The labeling of which is which (i.e., which are drivers and which are receivers) is largely a matter of choice. In FIG. 7, the elements that move signals away from the TESTER_IO node, toward one or more of the DUT_IO nodes, are referred to as “drivers”. The elements that move signals away from one or more of the DUT_IO nodes, toward the TESTER_IO node, are referred to as “receivers”. With this convention in mind, the channel I/O block 702 comprises an active driver 712, an active receiver 714, and a termination resistor 716. The input of the active driver 712 is coupled to the TESTER_IO node, and the output of the active driver 712 is coupled to the inputs of active drivers 718, 720, 722, 724 in each of the DUT I/O blocks 704, 706, 708, 710. Via a multiplexer 726, the input of the active receiver 714 is selectively coupled to the outputs of active receivers 728, 730, 732, 734 in each of the DUT I/O blocks 704, 706, 708, 710. The output of the active receiver 714 is coupled to the TESTER_IO node via the termination resistor 716.
Each of the DUT I/O blocks 704, 706, 708, 710 comprises an active driver (e.g., driver 718), an active receiver (e.g., receiver 728), and a termination resistor (e.g., resistor 736). The output of the active driver in each DUT I/O block is coupled, via a respective termination resistor, to one of the plurality of DUT_IO nodes. Also coupled to each of the DUT_IO nodes is a respective input of one of the active receivers.
In operation, a signal received at the TESTER_IO node of the parallel test circuit 700 may be fanned out to any or all of the DUT_IO nodes, or signals read at any of the DUT_IO nodes may be selectively transmitted back to the TESTER_IO node. In some cases, and as described in the '378 application, the parallel test circuit 700 may be augmented to provide for parallel reads from the DUT_IO nodes.
In theory, the parallel test circuits described in the '378 application can be expanded by coupling a single channel I/O block 702 to increasing numbers of DUT I/O blocks 704, 706, 708, 710, thereby increasing signal fan-out/fan-in by any number of signal paths (e.g., by 4, by 8, or by any other number of signal paths). In practice, however, it becomes more difficult to maintain signal integrity and DUT isolation as the fan-out/fan-in of a single parallel test circuit 700 is increased. For example, as more DUT I/O blocks 704, 706, 708, 710 are coupled to a single channel I/O block 702, it becomes more difficult to route signals between the DUT I/O blocks 704, 706, 708, 710 and the channel I/O block 702 such that like signal propagation characteristics are maintained amongst the different signal routes.
Even if the fan-out/fan-in of a single parallel test circuit can be increased while maintaining signal integrity, there are applications in which this might not be desirable. For example, a parallel test circuit with increased fan-out/fan-in may be less useful, or even cost-prohibitive, in applications where the increased fan-out/fan-in is not always needed (or not needed at all). As a result, it sometimes desirable to balance 1) the increased fan-out/fan-in needs of some applications, with 2) the modularity that lower order fan-out/fan-in circuits provide.